1. Field of the Invention
The present invention relates generally to the field of integrated circuit manufacturing, and more specifically, to methods and structures for providing isolation between circuit elements.
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of transistors onto a single integrated circuit (IC). In order to reach these levels of integration all the elements that go into such an IC must be shrunk. It is well known in the field of integrated circuit manufacturing that it is desirable to reduce the size of the transistors and interconnect lines that make up the bulk of an integrated circuit. However, modem metal-oxide-semiconductor (MOS) integrated circuits have also addressed the design and implementation of isolation structures to increase the density of ICs.
The state of the art isolation scheme in manufacturing of integrated circuits is to use shallow dielectric trenches to electrically separate neighboring transistors. Trenches are fabricated by a sequence of etching the silicon substrate, filling the trench with dielectric material, and planarization of the entire substrate by chemical mechanical polishing. The isolation performance of the shallow-trench isolation directly depends on the trench depth. Generally, the deeper the trenches, the better the isolation. However, as the packing density continues to increase, the lateral dimension of the trenches continues to decrease in ultra-large-scale integrated circuits. In order to achieve a manufacture-worthy process, the aspect ratio of the trenches, and therefore the depth of the trenches, is limited due to the limitations of the trench etching, filling, and polishing operations. This in turn compromises the isolation performance, and imposes an extra limitation to the process development.
Accordingly, there is a need for methods and structures to improve circuit density while maintaining appropriate electrical isolation between circuit elements.